1. Field of the Invention
The present invention relates to devices formed on semiconductor regions having doping profiles designed to adjust the operating characteristics of the device, and to the methods of making such devices.
2. Description of the Related Art
When forming MOS devices, it is conventional to form a buried channel by doping the channel region of the MOS device to adjust the threshold of the MOS device. One type of buried channel used in PMOS devices is formed as illustrated in FIGS. 1-3. In FIG. 1, an N-type substrate 10 has a 100-500 .ANG. thick sacrificial oxide layer 12 formed on its surface. The threshold adjust implant is made through the sacrificial oxide into the substrate 10. The threshold adjust implant may, for example, consist of a boron fluoride (BF.sub.2) implant at a dosage of 5.times.10.sup.11 to 1.times.10.sup.13 per cm.sup.2 with an energy of 30-70 KeV. For those device configurations which require an implantation to prevent punchthrough, an antipunchthrough implant is performed next. First, photoresist is deposited and patterned to define the region for the antipunchthrough implant. Then, phosphorus ions are implanted into the substrate at a dosage of 5.times.10.sup.11 to 1.times.10.sup.13 per cm.sup.2 with an energy of 50-250 KeV. The antipunchthrough implant mask is then removed. Regardless of whether an antipunchthrough implant is made or not, the sacrificial oxide 12 is then removed.
Referring to FIG. 2, a layer of thermal oxide 14 is grown to a thickness of 50-150 .ANG. on the substrate 10 to serve as a gate oxide layer. A layer of polysilicon 16 is deposited to a thickness of 2000-4000 .ANG., for use in forming the gate of the PMOS device. Phosphorus ions are implanted into the polysilicon layer 16 and then annealed to thermally activate the implanted dopants. If it is desired, a refractory metal or silicide layer such as WSi.sub.x or TiSi.sub.x is then formed on top of the polysilicon to reduce the resistance of the gate electrode material. As shown in FIG. 3, a photoresist layer is deposited on the polysilicon, and other layers if present, and the photoresist is patterned to form a gate mask 18. The polysilicon layer 16 is then etched and processing continues to complete the PMOS device.
CMOS devices consist of a PMOS device and an NMOS device. Performance of both PMOS and NMOS devices typically must be improved to achieve improved CMOS performance. Two problems are of particular concern for improving the performance and reducing the size of MOS devices: the short-channel effect and the segregation of dopants into the gate oxide. It is generally desirable to use a shallow buried channel doping region to avoid the short channel effect, but conventional implantation techniques often have difficulty in reliably producing a suitable channel doping profile. Typically, low energy implantations are used to define a shallow threshold adjust doping profile but such implantations are difficult to control and so are not well suited to mass production. Accordingly, a more readily controlled shallow doping process is desirable.
Conventional attempts to address the segregation of channel dopants into the gate oxide have significant drawbacks. Segregation of dopants from the channel region of the MOS device into the gate oxide may occur during growth of the gate oxide or during other high temperature processes like anneals. To avoid this, low temperature gate oxides are often used in making MOS devices. Such low temperature gate oxides are undesirable because those oxides are of poorer quality and are more prone to pinholes than are oxides grown at higher temperatures. Accordingly, it would be desirable to manufacture MOS devices in a manner compatible with the use of higher temperature gate oxides.